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Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /DMA2_SEC /DMA_INTCLR

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Interpret as DMA_INTCLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IRQ_CLR

Description

Interrupt Clear Register

Fields

IRQ_CLR

Controls the clearing of the IRQ outputs:

  • Bit [N] = 0x0: The status of IRQ[N] does not change.
  • Bit [N] = 0x1: The DMAC sets IRQ[N] low if the DMA_INTEN register programs the DMAC to signal an interrupt. Otherwise, the status of IRQ[N] does not change (see DMA_INTEN register).

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data